Design of 4H SiC CMOS logic gates and sequential circuits

Art der Arbeit

Forschungsarbeit

Bearbeiter

Vishvas Nanjunda Swamy

Beschreibung der Arbeit

This project aims to design, simulate, and optimize basic logic gates and sequential circuits, establishing a foundation for complex digital systems functioning reliably at temperatures up to 500°C. Core objec-tives include the design of essential CMOS logic gates such as inverters, NAND, NOR, AND, and OR gates, as well as sequential circuits (e.g. flip-flops, latches). These components serve as the building blocks for memory and state-holding functions in digital circuits. A significant challenge is optimizing these designs to maintain functionality at high temperatures, addressing issues like threshold voltage shifts and mobility degradation.Simulation and analysis will be conducted using SPICE models within Cadence Virtuoso and Spectre environments. The simulation goals encompass DC analysis to evaluate voltage transfer characteristics, transient analysis to assess dynamic performance metrics such as rise/fall times and propagation delays, and power consumption analysis to quantify static and dynamic dissipation, particularly under high-temperature conditions.

Ansprechpartner

Schraml, Michael (IISB, michael.schraml@iisb.fraunhofer.de)

Prof. Dr.-Ing. habil. Jörg Schulze