FA: Design of 4H SiC CMOS logic gates and sequential circuits

4. Dezember 2025

Vishvas Nanjunda Swamy –

Wide bandgap semiconductor, particularly Silicon Carbide (SiC), based electronic devices and circuits are presently being developed for use in hightemperature, high-power, and high-radiation conditions under which conventional semiconductors cannot adequately perform[1]. This study highlights the trade-offs between power efficiency, speed, and area. Utilizing the second generation of the process design kit (PDK) for Fraunhofer IISB’s 2 μm 4H-SiC CMOS technology in the Cadence® Virtuoso® toolkit, we examine a variety of logic circuits, such as Inverter, NAND, NOR, XOR and a sequential SR Latch focusing on their dynamic and transient analyses. Key performance metrics analyzed include energy per cycle consumption, total energy consumption, rise & fall time delays, total delay, rise time and fall time characteristics. The analysis demonstrates reliable operation at temperatures ranging from 27°C to 500 °C, addressing challenges such as voltage shifts, mobility degradation, and leakage currents, while evaluating the impact of different load capacitances on fan-out considerations for each logic gate. By adjusting the aspect ratio, trade-offs between power efficiency, speed, and area were optimized, resulting in minimized delay and energy consumption.

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