1. April 2026

MA: Optimization of Superjunction MOSFET Dynamics

Student: Vishvas Nanjunda Swamy

Summary

Superjunction devices have already demonstrated in silicon technologies that the previous “silicon limit” can be exceeded. They allow for a smaller chip area per device and/or a reduction of the on-resistance compared to conventional designs at the same design voltage. The industry is increasingly moving towards silicon carbide (SiC) for high-voltage applications. Due to the similarities between the two technologies, it is expected that superjunction concepts will also prevail in SiC.

The main goal of superjunction designs is to reduce the drift resistance by splitting the tasks of the drift zone into conduction and blocking (for details see below). In MOSFET applications, however, not only conduction losses are relevant: especially during dynamic switching, additional loss mechanisms come into play. Although the superjunction principle generally reduces the output capacitance compared to conventional drift-zone designs, this potential must be weighed against conduction losses, as design decisions in this area are to some extent in conflict with each other. The goal of this work is to demonstrate an optimization loop that enables the derivation of a device design for specific applications that optimizes both conduction and dynamic losses.

Objektives of the Work

Main Goal

Demonstration of an optimization loop to reduce the power losses of silicon carbide superjunction MOSFET designs for traction drives and battery charging applications.

Subgoals

Development of an understanding of the dynamic behavior of superjunction devices and identification and evaluation of dynamic loss factors of silicon carbide superjunction MOSFETs
Untersuchung von Konzepten zur Optimierung der Dynamik mittels TCAD-Modellen und anschließender Charakterisierung mit der Doppelimpulsmethode
Erstellung eines exemplarischen SPICE-Modells eines Traktionswechselrichters sowie eines AC- bzw. DC/DC‑Wandlers, das die Integration eines aus dem TCAD-Modell abgeleiteten Kompaktmodells ermöglicht
Entwicklung und Demonstration einer Optimierungsschleife zwischen dem Bauelementmodell und dem Applikationsmodell
Stretch goal: Integration of a thermomechanical model into the loop

Technical Background: Superjunction

Simplified, the blocking capability of a PN junction is related to the width of the space charge region according to the relation:

U_\text{BC} \approx E_\text{crit} \cdot d_\text{SCR}

In conventional MOSFET designs, the space charge region starts to form at the junction of the body and the drift region as a one-dimensional front and expands proportionally with the reverse voltage. Superjunction changes the geometry of the junction to form a second front along which the space charge region expands with increasing reverse voltage. One of the fronts moves vertical as in conventional junction structures, while the second front moves lateral. As can be seen in the illustration below, at a high enough reverse voltage the lateral fronts will meet, causing the space charge region to increase in size significantly, making it much wider than normal for the given reverse voltage.

In conventional MOSFET designs, the size of the space charge region can be tuned via the doping concentration of the drift region following:

d_{\mathrm{SCR}} \propto \sqrt{\frac{1}{N_A} + \frac{1}{N_D}}

But this causes the resistance of the drift layer to increase in proportion. Since the width of the space charge region in the superjunction concept is additionally increased as a result of its geometry, higher doping of the drift region becomes possible, in turn lowering drift resistance. Chip designs can use this freed budget to either lower on-resistance or chip size.

Illustration of the superjunction function principle. a) Expansion of a space charge region with increasing reverse voltage. b) Simplified parasitic capacitances in a MOSFET. c) Simplified forward resistance in a MOSFET.