Description

Superjunction devices have already demonstrated in silicon technologies that the previous “silicon limit” can be exceeded. They allow for a smaller chip area per device and/or a reduction of the on-resistance compared to conventional designs at the same design voltage. The industry is increasingly moving towards silicon carbide (SiC) for high-voltage applications. Due to the similarities between the two technologies, it is expected that superjunction concepts will also prevail in SiC.

There material proporites allow SiC MOSFETs to be designed for higher voltage classes compared to Si witch have reached the “silicon limit”. With superjunction concepts SiC MOSFETs can push into even heigher classes. These high reveres voltages require new edge Termintion designs that inegrate well with superjunction structures. Goal of this work is to demonstrate novel edge termination concetps in superjunction jbs and pin diodes. Diodes are used as demonstrater to allow for faster development since less process steps are required compared to a full MOSFET.

Objectives of the Thesis

Main Goal

Demonstration of novel edge termination concept for superjunction SiC MOSFETs on superjunction SiC Diodes as demonstrator

Subgoals

• Development of an understanding of the function of edge termination in silicon carbide superjunction MOSFETs
• Investigation of concepts using TCAD models followed by design of elected designs
• Strech goal: Manifactoring of demonstators

Technical Background: Superjunction

Simplified, the blocking capability of a PN junction is related to the width of the space charge region according to the relation:

U_\text{BC} \approx E_\text{crit} \cdot d_\text{SCR}

In conventional MOSFET designs, the space charge region starts to form at the junction of the body and the drift region as a one-dimensional front and expands proportionally with the reverse voltage. Superjunction changes the geometry of the junction to form a second front along which the space charge region expands with increasing reverse voltage. One of the fronts moves vertical as in conventional junction structures, while the second front moves lateral. As can be seen in the illustration below, at a high enough reverse voltage the lateral fronts will meet, causing the space charge region to increase in size significantly, making it much wider than normal for the given reverse voltage.

In conventional MOSFET designs, the size of the space charge region can be tuned via the doping concentration of the drift region following:

d_{\mathrm{SCR}} \propto \sqrt{\frac{1}{N_A} + \frac{1}{N_D}}

But this causes the resistance of the drift layer to increase in proportion. Since the width of the space charge region in the superjunction concept is additionally increased as a result of its geometry, higher doping of the drift region becomes possible, in turn lowering drift resistance. Chip designs can use this freed budget to either lower on-resistance or chip size.

Illustration of the superjunction function principle. a) Expansion of a space charge region with increasing reverse voltage. b) Simplified parasitic capacitances in a MOSFET. c) Simplified forward resistance in a MOSFET.

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