Prof. Dr.-Ing. Jörg Schulze

Eine Verringerung der Schaltzeiten von Leistungshalbleitern isteine wesentliche Maßnahme zur Reduzierung der Schaltverluste inLeistungsmodulen in denen (U)WBG-Transistoren genutzt werden. In konventionellenModulen können jedoch parasitäre Induktivitäten durch hohe Schaltgeschwindigkeitenzu Überspannungsspitzen und „Ringing“-Effekten führen, welche Schäden andererBauelemente im Leistungsmodul zur Folge haben können. Ein dissipativer,monolithisch in Silizium integrierter, RC-Snubber (in Reihe geschalteter Widerstand R und Kondensator C) kann solche Überspannungen absorbierenund Oszillationen effektiv dämpfen, was Schäden verhindern und kürzereSchaltzeiten ermöglichen kann. Solche Si RC-Snubber können direkt in dasLeistungsmodul integriert werden, was die Nutzung konventioneller Modulaufbautenund Wärmemanagement ermöglicht.

Durch eine Lochstrukturierung des Siliziums kann die effektiveOberfläche und damit die Kapazität des Kondensators vergrößert werden. Bei derAbscheidung der dielektrischen Schichten (Siliziumdioxid, stöchiometrisches und „stressfreies“Siliziumnitrid) auf diese Oberfläche entstehen jedoch hohe thermo-mechanischeSpannungen, welche die Siliziumhalbleiterscheibe verbiegen können und einenProzessierung erschweren oder unmöglich machen. Bei einer Erhöhung der Durchschlagsfestigkeitbei gleichbleibender Integrationsdichte (Kapazität), muss außerdem gleichzeitigdie Dicke der dielektrischen Schicht als auch die Oberflächenvergrößerung, alsoLochtiefe, erhöht werden, was zu noch größeren Spannungen führt. Um dieseProblematik zu lösen, soll in diesem Projekt ein neuer dielektrischer Schichtstapelbestehend aus thermisch gewachsenen Siliziumdioxid und stöchiometrischenSiliziumnitrid so designt werden, dass die mechanischen Spannungen reduziertwerden und eine Herstellung der RC-Snubber mit erhöhter Durchbruchfestigkeit ermöglichtwird. Gleichzeitig soll der Ladungsträgertransport durch die einzelnenSchichten, sowie den gesamten Schichtstapel, inklusive eingefanger Ladungen unddie Verteilung des elektrischen Feldes verstanden und analytisch modelliertwerden.

Abstract (fachliche Beschreibung)

Herstellung und Charakterisierung von SiGeSn-„Pillar“-MOSFETs

Abstract (fachliche Beschreibung) des Projektes "Herstellung und Charakterisierung von Bipolarbauelementen auf 4H-SiC a-Plane Wafern zur Funktionalisierung von Siliziumvakanzen für Quantenanwendungen"

Abstract zu:

Towards reliable high-temperature stable SiC CMOS technology - concepts, challenges and solutions

The rapidly expanding SiC market requires theinstallation of large production capacities for the manufacture of SiC crystalsand SiC devices. This is also associated with a large demand for graphitecomponents, which are subject to a great deal of wear during the growth processesof the SiC crystals and epitaxial layers. The introduction of high temperatureand corrosion resistant protective coatings based on tantalum carbide (TaC) canhelp to save resources, deescalate supply shortage and reduce costs. Inaddition, protective TaC coatings could help improve process stability and thusmaterial quality and yield. This thesis presents the development of analternative slurry-based spray coating approach which has the advantage over allsorts of different coating technology routes like thermal spraying, electro deposition,carbonization, sol-gel method, sputtering and especially compare to conventionalchemical vapour deposition (CVD). With our technology approach it is possible tocoat components of any size and geometry, to adjust the coating properties overa wide range, such as thickness, density, composition, and even to repair a componentin defective areas after it has been used in application.

The slurry-based spray coating technology starts withmanufacturing a stable suspension, proceeds with creating a homogeneous spraycoated layer on top of the graphite substrate with hardly any structuraldefects like lunkers, etc. and ends with a sintering process to generate thefunctional TaC coating with distinctive structural and mechanical properties.

In general, there are three main requirements to thecoating as a protective layer itself which should be fulfilled. First, thecoating should be homogenous and smooth so there are no weak points for a concentratedassault of reactive gases. Second, a strongly adherent coating is necessary forprotection over a certain amount of time, especially in a harsh hightemperature environment. Finally, to protect the components to its full extentthe coating has to be crack-free, thick, and less porous, to act as afunctional separation layer.

Using the right mixture of selected ingredients, includingfine powder with a distinct particle size distribution, water, a dispersingagent, a binding agent and a defoamer, it is possible to create a defect-free spraycoating layer on graphite with a perfectly homogenous particle distribution. Dueto a fundamental and systematic investigation using graphite materials withdifferent properties, especially open pore morphology, it was possible to identifygraphites with surface pore structures which can be coated smooth and homogeneouslywithout any depressions. By using the coating procedure repeatedly, thisalternative approach, compared to conventional CVD process, can create thickcoatings up to 300µm with hardly to no effort. But thicker coatings tend todelaminate easier if the surface bonding is not sufficient. For that reason,the bonding strength and wear resistance of the coating was tested fordifferent coating thicknesses by a standardized pull-off test and scratch testsetup. Another important parameter is the difference in thermal expansioncoefficient between the TaC coating and the graphite component which should beas small as possible to avoid cracks, that could also lead in delamination andeventual failure under application environments. The sintering conditionsdefines the porosity of the coating and is also evaluated.

To finally evaluate the performance of the coatingunder real application conditions, small pieces of graphite were coated allaround and were put in a reactor chamber to test them under industrial physicalvapour transport (PVT) SiC growing conditions. It is demonstrated that thecoating on specific selected graphite materials including the right coatingproperties can withstand the harsh high temperature growing conditions and isalso suitable for use in SiC epitaxy. In addition to basic investigations,results on real components as used in the PVT and epitaxy process will also bepresented. Results on the variation of process times in the PVT process and therepeated use of coated components are done.

Abstract zu:

Novel Approach to SIC Power Device Fabrication: High-Purity Semi-insulating Substrates Doped by Energy-Filtered Ion Implantation

The research project is being worked on as part of an LEB PhD project in collaboration with the Fraunhofer Institute of Integrated Systems and Device Technology.

The semiconductor electronics field has come a long way in the past century and is only going to grow by leaps and bounds. The very first semiconductor device can be traced back to the rectifier (AC-DC converter)that was invented way back in 1874. The building blocks of today's semiconductor devices are the transistors and they were invented much later in the year 1947 by Bardeen and Brattain at Bell Laboratories, USA. The semiconductor industry has evolved quite a lot since due to various advancements in technology and has transitioned to the integrated circuit (IC) era. These ICs have made their way into a wide variety of electronic products ranging from the humble calculator to electric vehicles (EVs) and also to more advanced technologies like that of a space rocket launch system. The metal-oxide-semiconductor field-effect transistor (MOSFET) is the most commonly used type of field-effect transistor (FET) that makes up current generation ICs. There can be billions of these MOSFETS on microprocessor devices such as the latest one from Apple. The wonderful field of photolithography has made it possible to manufacture these transistors that are known to be the building blocks of semiconductor devices. State-of-the-art clean rooms with very low levels of contamination and newer lithography techniques have allowed for the manufacture of semiconductors in a fewer number of steps to keep up with the demand of the industry. The path towards achieving a large number of transistors on a chip has become quite challenging of late due to the processes employed. Smaller features require a light source with a lower wavelength, which in turn can make manufacturing difficult and less predictable. The major bottleneck in the process is now the pattern transfer from the mask to the wafer. This is mainly due to the various chemical, optical and mechanical effects taking place within the photoresist polymer. The feature shapes and contours may not always match the design specifications of the mask due to these effects. Such defects can considerably reduce the throughput of the lithographic system and lead to losses in process productivity and increase costs. Various complex correction measures are employed to help mitigate these defects. Good defect prediction models need to be developed and implemented in order to predict and understand their occurrences. Moreover, defects in modern extreme ultraviolet lithography (EUV) do not scale with the feature size. The defects can therefore be in the range of several nanometers, which make them quite large to neglect. Many of the lithographic simulators do not have the means to correctly and accurately predict all the outcomes of the numerous lithographic processes. Since lithography is a vast field encompassing a number of scientific areas ranging from optical physics, chemistry, mathematics and mechanics, modelling and simulating a complete process till the final stage can be very challenging. Compact models have been used in the past as a compromise to help balance the performance and accuracy requirements in order to suit the needs of the industry. These models however can fall short in terms of accuracy while being quite good when it comes to performance. There is therefore a need to model certain aspects of the lithographic process using rigorously models and combine them with a compact/faster model for certain processes to make a trade-off in the simulator. Computational methods can greatly help in better understanding the impact of various process settings on the final outcome of the lithographic process. Process and parameter optimizations can be carried out without spending too much effort and time to get the results. Simulations play a key role in processes that are less deterministic in nature or are influenced by a number of different outcomes. This makes photoresist process simulation quite formidable since it is the final stage of lithographic processing and is therefore influenced by all the prior processes. To maintain pace with the growing demands of the semiconductor industry, more complex or otherwise unexplored aspects of photoresist processing need to investigated. Negative-tone development (NTD) methods in conjunction with bright field masks have become a mainstay in lithography due to various benefits with regards to image contrast and line width roughness (LWR). With the growing usage of the NTD process lithographers are being confronted with a number of challenges. Resists that are subjected to NTD are susceptible to a variety of undesirable effects like shrinkage during the post-exposure bake (PEB), deformation, variable development rates and pattern collapse. These issues need to be tackled or mitigated to help in the further progression of EUVL. A number of simulation models and algorithms need to be developed in order to correctly predict and analyse the defects encountered. The main objective of this thesis is to model, simulate and predict a diverse set of nano-mechanical effects seen in photoresist materials. A number of photoresist effects leading to some form of deformation are observed right from the exposure step. A finite element method (FEM) based model is developed to help simulate the shrinkage and volume losses seen in NTD resists. This new model uses a relational principle where the protection group concentration is analogized with the thermal expansion coefficient during the PEB step. Additional fitting parameters like the shrink factor are then used in the model along with the crucial material properties comprising of the Young's modulus, Poisson's ratio and density. The shrinkage affects the critical dimension (CD), height and volume of the final photoresist profile greatly and is the main source of the overall dimensional disparity. The protection group concentration values along with the various light and chemical composition profiles are extracted from simulations performed using the lithography simulator Dr.LiTHO developed at Fraunhofer IISB. The results obtained from this simulator are used as an input to the more rigorous FEM deformation models developed in this thesis. The deformation during PEB also leaves a certain amount of stress and strain within the bulk of the resist which contributes to further deformation during the development step. Another model is developed to help understand this effect seen from experimental data. The standard kinetic development rate model does not capture the influence of strain on the overall development rate. A newer improved version for the development rate which incorporates the impact of strain and prior deformation is established. Strained regions could lead to localized areas with higher development rates that cause variations in CDs and profile contours. A combination of mechanical, chemical and optical proximity effects gives rise to these more complex defects in NTD resists. After development there is a change in boundary conditions, i.e. the resist material is washed away leaving behind a free-standing feature. This free-standing feature depending on the dimensions, shape and feature density can begin to gradually relax due to a gradual decrease in the residual stresses. A model simulating this behaviour is introduced to help predict the extent of sidewall angle and CD changes occurring.

After the resist undergoes a chemical development, a rinsing of the resist surface is carried out before the final etching step. The chemical developer liquid dissolves parts of the resist and can leave residues on the final pattern above the substrate. The rinse liquid (usually water) is therefore used to get rid of the residual developer present on the resist profile and keep it clear of contaminants. There is however an issue with this procedure which can lead to pattern bending and collapse. There is a possibility that the rinse liquid does not dry evenly due to the shape and layout of the overall pattern. The surface tension of the rinse liquid could in turn cause the resist pattern to collapse. The presence of an underlayer or hardmask in EUVL adds another element of risk to the stability of the pattern. Resist debonding or delamination can be induced as a result of the lack of adhesion with the underlayer. This effect along with pattern bending is modelled for the two most prominent use cases, namely lines and spaces and pillar shaped patterns. Pattern collapse in previous generation deep ultraviolet lithography (DUVL) was mainly caused due to the higher aspect ratios of the patterns which can negatively impact its mechanical stability. In EUVL however, there are a different set of reasons responsible for this problem. Resist features in EUVL however have lower aspect ratios but the material is generally much softer and can also suffer due to lower adhesion with the substrate/underlayer and line width roughness (LWR) arising due to a variety of stochastic effects. The standard model used to simulate pattern collapse in DUVL would therefore not suffice to simulate the same in EUVL. Localized regions of higher aspects ratios and higher feature densities arising from LWR can make the modelling of collapse and feature bending much more challenging. To circumvent this issue, a machine learning based approach was used and a large amount of data was generated to train a network to predict collapse probabilities for resists with varying degrees of roughness emanating due to stochastics. The rough profiles for the one-dimensional lines and spaces feature can be represented by using a combination of power spectral density (PSD) functions with parameters calibrated against experimental data.

A trench gate MOSFET is a promising alternative power device to the conventional VDMOS structure. In principle, the n+-source and p-well regions are implanted in the entire active area.  Subsequently, trench structures are formed into this implanted area. Whereas maximal alignment accuracy can be obtained, a drawback of trench-last process is the difficulty to control the etching behavior of the implanted 4H-SiC, which is strongly dependent on the doping concentration Therefore, the manufacturing process, in which a formation of trenches is followed by self-aligned n+-source and p-well implantation (trench-first process), is proposed to form curved trench geometry by a reshape process for reducing high dielectric field concentration at trench bottom corners.

In this work, the design and manufacturing process of devices with trench-first process is investigated based on the modeling by using TCAD process- and device simulation for enhancement of electrical performance. Simultaneously, the research effort in process integration is described with a focus on the process and design activities, e.g., novel trench gate oxide module to obtain the high reliability and interface quality. Overall, this self-aligned trench-first concept offers greater flexibility during the research and development phase.

Addressingtemperature ranges between room temperature and 500 °C places multiplechallenges on the devices and thus the technology used to fabricate them. Asthese have yet to be completely solved, several points must be optimized fromits current state. 

The electrical contact between SiC and themetallization must be optimized to behave ohmic within the whole temperaturerange for both NMOS and PMOS. Therefore, the size of the contact vias alsobecome relevant, as well as the contact materials and the silicidation process.Metallization and passivation layers must withstand the harsh environment,including the high temperature. Ideally, a second metal layer must be availableto provide routing options for more complex integrated circuits. Also, thetechnology must be adjustable within certain degree depending on specialrequirements of customers and applications without impacting its reliability.One such example could be threshold voltage adjustment. All these points needto be solved to contribute this technology platform for further scientificresearch. With it, it would be possible to fabricate different sensor types, including on-chip readout electronics, which can for example be used in gas turbines or aircraft and rocket engines to monitor multiple parameters. 

This work aims to enable a high-temperature stable 4H-SiCtechnology to fabricate CMOS devices. To accomplish this, existing processmodules will be extended, and novel ones created. These will be modularly integrateable into the process flow. Fabricated process control structures and singletransistors will be characterized to extract material and devicecharacteristics and to further optimize them.

Vertical power devices based on GaN-on-Si(111) potentially offer several advantages over their lateral counterpart, i.a., superior thermal management, higher reliability, and the capability of achieving high breakdown voltage and current density without increasing the chip size [1]. In addition, Si is attractive, due to the large diameter availability, low cost and good thermal conductivity compared to other substrates. However, for device operation at high voltage (> 1 kV), several micrometers of high quality GaN must be deposited. This is a major challenge as lattice and thermal mismatch lead to severe wafer curvature and eventually cracks if not properly controlled. Further, a wafer bow < ±50 µm is required for processing in a conventional CMOS line [2]. In case of substrate diameters beyond the state of the art this issue becomes even more critical, since the bow typically increases with the square of the wafer diameter. Recently the market trend for GaN-on-Si(111) is moving from 150 mm to 200 mm and development towards 300 mm is visible. Thus, a further optimized epitaxy and a model to predict the wafer bow is essential.  
The target of this thesis is to provide GaN-on-Si(111) epi-stacks grown on 8” substrates which have the desired properties to fabricate power transistors with a breakdown voltage of ~1200V and a specific on-resistance of < 4 mΩ cm2. In addition, a curvature model will be developed to predict the curvature evolution during growth and after cooling based on the epitaxy process. [1] Y. Zhang, M. Sun, Z. Liu, D. Piedra, H. Lee, F. Gao, T. Fujishima, T. Palacios, IEEE Trans. Electron Devices, 60, 2224–2230 (2013). [2] M. Ishida, T. Ueda, T. Tanaka, D. Ueda, IEEE Trans. Electron Devices, 60, 3053–3059 (2013).

Funktionalisierung des Tunneleffekts für neuartige Leistungstransistorkonzepte

Context: The push to miniaturize transistors on the chipshas been a direct measure of success for the semiconductor industry since thelate 1970s. Smaller transistors have lower energy consumption and provide theoption to either increase the transistor count on the same chip size or toreduce the chip size. This progress follows Moore’s Law, which states that thenumber of transistors on a chip doubles every 18 months. The latest technologyin optical lithography is the EUVL (extreme-ultraviolet lithography).  

This work focuses on the EUV wavelengthof 13.5 nm with high-NA of 0.55. This system is to be used in high scalemanufacturing by end of 2023 as planned by ASML for EXE-5200 tool.

Aim: The focus of this thesis is the mask effects on theresulting aerial images. As the printed features gets smaller approaching thelimits of the system, the effects of the optical constants of the mask on theimage increases. Increased sensitivity in imaging metrics is observed for lowrefractive indices (n) and extinction coefficients (k).

Approach: The governing physical concepts of lightpropagation inside the mask absorber are investigated. The waveguiding effectof the mask absorber is proven and its consequences shown. The reflectivemultilayer reflectivity curve is divided into regions and the effect of theregions on the aerial image. A genetic optimization algorithm is used to findthe optimal multilayer material and duty ratio between its constructingmaterials in terms of imaging metrics. The effects of the mask absorber andmultilayer are separated via the hybrid mask model. The interaction between theabsorber and the multilayer is important to reach the optimal EUV mask.

Results: Waveguiding effect governs the light propagationinside the mask absorber. The role of the excited waveguide modes in the maskabsorber opening is explained. The coupling between diffraction orders due toexcited perpendicular waveguide modes causes a drop in image contrast. Theeffect of refractive index and extinction coefficient in mitigating thecoupling effect is detailed. Higher extinction coefficient is favorable forimaging as it suppresses the coupling effect and reduces the image shiftbetween single pole images. The reflective multilayer impacts the imagingperformance. widening the bandwidth of the reflective multilayer is not theoptimal solution for the image contrast. The effective reflective plane insidethe reflective multilayer changes the mask 3D (M3D) effects in the image. RuSimultilayers exhibit lower M3D effects compared with MoSi counterparts.  The hybrid mask model is used to correlatethe imaging metrics variations with mask components and optical constants. Thehybrid model is used to explain the effects of the double diffractionphenomenon in EUVL. The effects of the multilayer are explored. The sensitivityin low refractive index and low extinction materials is shown. The usage oftransmission and phase of a mask absorber is proven to be misleading, howeverthe usage of n, k, and thickness of the absorber is more accurate. Sametransmission and phase absorber can behave differently according to thecorresponding optical constants and thicknesses.

Conclusion: Optical constants (n and k) is moreimportant than phase and transmission of the mask absorber in finding theperfect EUV mask. Waveguiding effect causes a coupling between the diffractionorders, which causes a drop in the image intensity. Optimizing the reflectivemultilayer require imaging metrics as objectives instead of traditionally usedreflectivity bandwidth maximizing objectives. The effective reflective planeinside the multilayer plays a major role in mitigating the telecentric errorsin the image. Identifying the absorber using phase and transmission isinaccurate and should be avoided. Dark-field (lines) images have lesssensitivity to variation in bias and optical constants compared to bright field(spaces) images.

The thin film metallization, as a key structure of the semiconductor devices, realizes the bond-ability of the chips on circuit carriers and directly influences the electrical and mechanical reliability of the interconnection. One of the reliability issues of thin film metallization is delamination due to its adhesion strength degradation in operation. To investigate the degradation behavior of the thin film metallization, its adhesion strength needs to be quantitatively characterized.

In a previous study, a recently developed method, cross-sectional nanoindentations (CSN), has been utilized to characterize the adhesion strength of the brittle thin film quantitatively. With the help of elastic plate theory, the strain energy release rate of the thin film which is the required specific elastic strain energy to result in delamination can be calculated. However, due to the high ductility of the metal, the current technology is not suitable for thin film metallization.

In this project, a combined experimental and numerical approach is developed. In the experiment, the thin film is tested by CSN and its delamination behavior is statistically analyzed. In the finite-element model, the plastic dissipation of the thin film is separately considered during the delamination. By using the CSN-induced crack profiles from the experiment, the parameters of the cohesive zone model in simulation which can describe the thin film adhesion strength can be inversely identified. Finally, with this approach, the adhesion strength degradation behavior of a standard thin film system in temperature cycling test (TCT) is investigated and characterized.

To builtflexible electronics the structural engineering of the metallic interconnectsis significantly important. Several concepts with different complexity areused. All concepts have in common to increase L₀ and consequentlyreduce the strain. The island-bridge concept is one well known possibility andis often used with buckled, arc-shaped interconnects (bridge). The buckling ofthe bridge can be reached by mounting islands together with the metalstructures onto are a pre-stretched flexible substrate and with releasing thestretch afterwards, so that the interconnects are partially lifted to form anarc shape. If the bridges have a sufficient height in the micrometer range, onedesign option is the buckling into the trench depth, which separates theislands from each other. Alternatively, before the actual process for theelectronic devices starts, a stretchable substrate with a buckled surface isproduced. This means a difficult transfer process or an extra manufacturingprocess is needed. 

The aim ofthis work is to develop an alternative production route based on theisland-bridge concept, where the free-standing interconnect is designed intothe trench depth and the manufacturing is integrated into standard siliconplanar technology.

The soproduced arrays combine simple shape design with the advantages of the islandbridge concept. For the first time the production of buckled metal structuresis fully integrated into well known standard production steps without neitherthe need of a difficult transfer of the structure onto a stretchable substratenor the additional pre-production of specific buckled substrate.

The purpose of this project is to explore the capabilities of deeplearning models for EUV lithography simulations and utilize them to speed-up avariety of computationally intensive applications. An objective of this project is the developmentof accurate and efficient data driven deep learning models for EUV lithographicimaging. The developed deep learning models are applied to EUV lithography settings including demonstration of potential advantages and comparison compared to rigorous physical simulation models. Furthermore, optimizations of the deep learning model’s data efficiency to minimize the training data requirement for EUV data using techniques such transfer learning and data selection are investigated. The developed frameworks are also applied for experimental data, including SEM images of wafers. This project also involves a demonstration of perspectives of deep learning models for computationally intensive optimization techniques such Source Mask Optimization (SMO), mask biasing or Optical Proximity Corrections (OPC).

Ausbeute spielt eine wichtige Rolle in der Halbleiterindustrie. In denletzten Jahren entwickelte sich auf dem Markt fürLeistungshalbleiterbauelemente ein immer stärker wachsender Anteil derHalbleitermaterialsystemen mit weiter Bandlücke, insbesondere Siliciumcarbid(SiC). Aufgrund seiner diversen Vorteile wird SiC immer wichtiger in derLeistungselektronik. In dieser, im Vergleich zur Silicium-Technologie, nochjungen Technologie, gibt es noch einige Mechanismen, die zu verringerterAusbeuten und verringerter Bauelement-Lebensdauer führen. Aufgrund derschnellen Weiterentwicklung sowie der speziellen Materialeigenschaften von SiC,ist vor allem die Ausbeute bei der Fertigung (und auch die Zuverlässigkeit derBauelemente) ein kritischer Faktor für eine effektive Kommerzialisierung vonSiC-basierten Leistungsbauelementen.

In dieser Arbeit werden unterschiedliche Aspekte der Ausbeuteerhöhung inder SiC Technologie beleuchtet. Dabei wird der Einfluss von unterschiedlichenPhänomenen bewertet und bezüglich ihrer Bedeutung eingeordnet. Ein wichtigerBestandteil der Analyse ist die Einbeziehung von Epitaxie-Defekten, derenEinfluss auf die Bauelementeigenschaften zum einen bekannt sein muss, um andereEffekte korrekt zu bewerten, zum anderen mit Fertigungsprozessen und derenProzessergebnissen in der VDMOS Technologie wechselwirken können. Es konntegezeigt werden, dass die untersuchten Punkte in Bezug auf die Qualität undQuantität speziell für die SiC-Technologie relevant sind. Die gefundenenEinflüsse betreffen die Auswirkungen von Epitaxie-Defekten auf das Sperr- und Durchlassverhaltenbei PiN-Dioden und den Effekt von Punktdefekten im SiC-Kristall auf Kanal- undSperreigenschaften durch Kompensationseffekte. Weiterhin die Abhängigkeiten derBauelementperformance und Prozessrobustheit vom Zell-Design in der VDMOS Technologie,vor allem im Zusammenhang mit durch Fehljustierung erzeugten Kurzkanaleffekte, sowiedie Auswirkungen von Epitaxie-Defekten und dem Gateoxid-Prozess auf dieAusbeute und Zuverlässigkeit des Gateoxids in der VDMOS Technologie. Zusätzlichwerden mögliche Gegenmaßnahmen aufgezeigt, um die Auswirkungen dieser Effektezu reduzieren und die Robustheit des Herstellungsprozesses zu erhöhen.

Im Rahmen des Forschungsprojekts soll eine halbleiterbasierte elektrische Sicherung entwickelt, hergestellt und charakterisiert werden. Hierfür wird zunächst mithilfe von analytischer und numerischer Modellierung eine (Bauelement-) Zelltopologie konzipiert, die zur monolithischen Integration des Prinzips "thyristor dual" geeignet ist. Da JFETs für die Umsetzung des "thyristor dual" von Vorteil sind, wird im Anschluss die Realisierbarkeit einer 4H-SiC JFET Technologie innerhalb der am LEB/IISB zur Verfügung stehenden Reinraumumgebung nachgewiesen. Die in diesem Zuge entwickelte JFET Technologie wird zur Herstellung von Prototypen verwendet, welche dann der elektrischen Charakterisierung des neuartigen Sicherungskonzeptes dienen. Die quasi-statischen und transienten Eigenschaften der Prototypen werden im finalen Schritt denen der Simulationsmodelle und des Standes-der-Technik gegenübergestellt und diskutiert.

In this work, nickel-based ohmic contacts were fabricated on the C-side of n-doped 4HSiC substrates using a short-time pulse laser, electrically characterized and analytically investigated to understand the underlying formation mechanisms compared to classical RTP. To obtain conclusions about the prevailing temperatures from the laser fluence used during alloying, a thermal simulation was created in COMSOL. This makes it possible to describe the silicidation mechanisms during laser processing in a temperature-dependent and thus system-independent manner.